12. Detailed Description of the Arithmetic Part (CA).
We shall divide the CA operations into a number of types. We shall make provision for 16 types, but for the present will only use nine. The types are distinguished by digits CI 5-8.
Type K. Pass the content of TS 6 into a given minor cycle.
Type L. Pass the content of a given minor cycle into TS 6.
Type M. Pass the content of a given TS into TS 6.
Type N. Pass the content of TS 6 into a given TS other than TS 4 or TS 5, or TS 8 or TS 1.
Type O. Pass the content of the first 12 minor cycles of a given DL out onto a card via the reproducer.
Type P. Pass the content of the card at present in the card reader on to a given DL.
Type Q. Pass CI 17-32 into TS 6.
Type R. Various logical operations and others yielding results forming one minor cycle, to be performed on the contents of TS 9 and TS 10 and transferred to TS 8.
Type S. Arithmetical operations yielding a result requiring more than one minor cycle for its retention. Results go into TS 4 and TS 5.
Type T. Stimulate a given valve element.
A trigger circuit is associated with each type. With the exception of Q these are all excited for a period consisting of a number of complete minor cycles beginning with a P1 and ending with a P32.
The main components of CA are the 32 temporary storages TS 1-32. Of these TS 1-12 have some special duties.
TS 1 is used to carry the retiring data, i.e. the CD which applied just before the last instruction of type B.
TS 2 and TS 3 contain the arguments for the purely arithmetical operations, or most of them, and for the logical operations.
TS 4 and 5 contain the results of the arithmetical operations. They are frequently connected up in series to form a DL 64. This is because the results of most of the arithmetical operations are sequences of more than 32 but not more than 64 digits.
TS 6 is used as a shunting station for the transfer of information from place to place.
TS 7 is used to carry the digits of a number m when it is proposed to multiply by 2m.
TS 8 is used to carry the result of logical operations and other operations not requiring more than one minor cycle.
TS 9 and TS 10 are the inputs for the logical operations.
TS 11 will usually be used in connection with error calculations, and accordingly has a special role in the production of multipliers.
TS 12 is used for the timing in ‘automatic’ multiplication and for the selection of unusual combinations of digits in the multiplier. The word ‘automatic’ is used because of an analogy from desk machines.
To decide between types K to T we use CI 5-8. Digits 5,6,7 are treod out to the valve elements TRG 000 . . . TRG 111, as in Fig. 23. These tree elements are each associated with two types, which are distinguished by CI 8. Thus TRG 000 would be identical with KvL if it were not for timing. For this timing we introduce CATIM which is to be stimulated during the appropriate time in CA operations. KvL is identical with TRG 000 & CATIM (Fig. 24).
In case K we pass the output of TS 6 to COMMIN and hence to the inputs of all the delay lines. We gate the appropriate one of those at the appropriate time, given by TIMCA by comparison of the output of the slow counter SCA with CI.
In case L we do somewhat similarly, passing the appropriate output to COMMOUT and thence to the input of TS 6 at the appropriate time given by TIMCA.
In case M we gate the appropriate output and pass into TS 6.
In case N we pass the output of TS 6 to the inputs of the other TS, only gating the one required.
In case O the first effect is to set the mechanism in motion to pass a card through the reproducer. By means of a commutator arrangement or otherwise the reproducer sends back a series of pulses which indicate the times when the reproducer punches are ready to accept current. In the circuit diagram (Fig. 25) two sets of pulses are shown which are intended to mark the beginnings and ends of these periods. They may be separately provided by the reproducer, or one may be derived from the other by delaying or otherwise. The two sets of pulses each control trigger limiters connected up so as to extinguish one another. (Do not confuse this with the two mutually extinguishing triodes that will normally form part of a trigger circuit or trigger limiter.) One of the trigger limiters TIMOUTCARD stimulates the trigger circuit OUTIM on the first admissible P 10. A pulse on the stimulation of OUTIM goes into a slow counter SCB and enables us to keep track of the number of rows of the card that have been punched. The content of SCB is compared with that of SCA and when they agree we know that the minor cycle which we wish to pass out is now available, and TIMCA is accordingly stimulated. TIMCA and OUTIM together permit COMMOUT to pass out to the trigger circuits OUT 1 . . . OUT 32 on which it is set up statically and controls the punches.
On the final exit of the card the reproducer sends back a signal to the calculator, which, in combination with O operates a trigger limiter CARDEXOUT. This suppresses CATIM and hence O. CARDEXOUT has feedback to suppress itself, and this will be successful because O will have been suppressed by the time it comes to act.
The behaviour in case P (input) is very similar. The chief difference is that whereas OUTIM was used to gate the output from the calculator INTIM is used to gate the input.
It should be noticed that a completely blank instruction has a definite meaning, viz. to pass the material on the card in the reader into DL 0000000000.
In Fig.27 TS 01101 typifies any of the TS as regards output connections shown on other diagrams. It is also typical as regards input connections, except as regards TS 4,5,8,1, which have no input connections except those shown on other diagrams.
In the case of operations of type R we shall calculate all of the expressions involved and select them by means of tree elements, digits 18 to 23 being used. The operations so far are:
Digits 000000 TS 8 = TS 9 & TS 10.
Digits 001000 TS 8 = TS 9 v TS 10.
Digits 010000 TS 8 = -TS 10.
Digits 011000 TS 8 = (TS 9 & TS 10) v (-TS 9 & -TS 10).
Digits 100000 TS 8 = 0.
As we shall have very much to say about type S we shall make a few remarks first about type T. In order to be able to obtain a rather direct access from the instructions to the valves we shall introduce a number of valve elements which can be stimulated to order. We may have 64 of these, say FLEX 000000 to FLEX 111111. The circuit will be simply as shown in Fig. 31. It is intended that the outputs of these valve elements should be connected in various ways into the circuit when it is desired to try out new circuit arrangements. It is thought that they may often provide means for doing things simply which could be done lengthily as an ITO. To an extent this represents a compromise between the new system of ‘control by paper’ and the old plugboard and soldering~iron techniques.
We shall also describe the timing arrangements before passing on to type S. We have already mentioned CATIM which determines the timing but we have still to mention what controls CATIM. CATIM is stimulated as soon as the first P1 appears after the signal A, or, in case Q, the first P17. It is extinguished by a variety of means. In cases K and L it is extinguished by the ending of TIMCA indicating that the required minor cycle has just passed through. In cases M, N, R, T, it is only permitted to last for one minor cycle. In case Q it is also only allowed to last for half a minor cycle. In cases O, P the extinguishing signal is CARDEX, which is given by the card reproducer or reader on the final exit of the card, via a trigger-limiter. In case S the signal comes from FINARITH.
The facilities provided under type S are not easily enumerated, because they do not consist of a number of different operations stimulated by different tree valve elements, as for instance applies in the case of the logical processes. Rather they are to be thought of as one process which can be modified in various ways. The standard process always involves converting the content of TS 4 and TS 5 into ‘series form’, i.e. instead of connecting the outputs of TS 4 and TS 5 to their own inputs they are connected to each other's. When they are so connected their content will be described as the ‘partial sum’. Some quantities are then added to or subtracted from the partial sum. If the quantity is to be added then POS is stimulated, otherwise they are subtracted. We may if we wish cancel the original partial sum before adding, in which case we must stimulate CANCEL for a period of two minor cycles. The quantity to be added or subtracted is expressible as the product of a quantity known as the ‘multiplicand’ and an integer which may be taken to lie in the range -7 to 15, positive values being the more normal. The multiplicand may be taken from TS 3 or from the partial sums register itself. This latter case is convenient for the purpose of multiplying the partial sum by a small integer without a complicated series of previous transfers; if the multiplicand is taken from the partial sums register then SELF is stimulated. The multiplier may also be taken from a variety of sources. It may be taken from TS 2 or from CI or from TS 11, and we accordingly stimulate NOR, GIV or ERR. The multiplier consists of four consecutive digits from whichever source is chosen. The choice of the digits is made by means of a choice of one of the pulses P1 to P32 to enter on a certain line (DIGIT). At present it is suggested that in case NOR this should be P1, resulting in the use of digits 1,2,3,4, in case IV it should be P 23 resulting in the use of digits 23,24,25,26, in case ERR1 it should be P 10, and in case ERR2 it should be P 14. In case DIFF these arrangements are to be overridden and the pulse will be stored in TS 12 and taken from there.
In case AUTO the above fundamental process is repeated eight times. In each repetition the multiplicand is taken from TS 3, but it is modified each time by multiplication by 24, this effect being obtained by allowing it to circulate in a DL34 during AUTO. We also wish to take different digits of the multiplier at each repetition of the process; this is done by taking our pulse from TS 12 but allowing it to circulate in a DL 34 also. Facilities are also provided for multiplying the partial sum by a power of 2. Although the circuits are arranged so that this could be combined with other operations, it is not intended that this should be done. The facility consists in enabling the partial sums to be delayed by any time up to 63 and passed through for a period of 2 or 3 minor cycles as desired. The amount of delay is taken from digits 1-5 of TS 7. We stimulate ROTATE 2 or ROTATE 3 according as we wish the rotation to last for 2 or 3 minor cycles.
It may be as well to describe how some rather definite operations are done.
Addition. We do not have a facility for addition of two given numbers so much as for the addition of a given number into the partial sum. To add the content of TS 3 into the partial sum we must stimulate S, POS, GIV, and must also set up the number 1 in columns 24-27. The multiplicand is then TS 3 and the multiplier is 1.
Subtraction. As addition but we do not stimulate POS.
Short multiplication (A). To multiply TS 3 by 6 (say) proceed as for addition with 0110 in columns 24-27 instead of 1000. We shall very likely also want to cancel the original content of the partial sums register and therefore stimulate CANCEL.
Short multiplication (B). To multiply the partial sum by 6 we must stimulate S, POS, CANCEL, SELF, GIV, and set up 0110 in CI 24-27.
Short multiplication (C). As B but do not cancel and put 1010 in CI 24-27.
Short multiplication with addition. We wish to multiply TS 3 by TS 2 and add into the partial sum. We stimulate POS, NOR, AUTO, DIFF.
Long multiplication with subtraction. If we wish to subtract from the partial sum we do not stimulate POS.
Division is an ITO and will probably be carried out by means of the recurrence relation μ0 = ¾, μn + 1 = μn(2 - aun). The limit of the sequence un is a-1 provided 1 < a < 2.
The appropriate instructions for these operations will be found in Fig. 37.
The content of TS 2 or TS 3 is best considered to be a binary integer, i.e. that the least significant digit is in the units position. We must also consider that the most significant digit has reversed sign. The least significant digit appears at time P1 and the most significant at P32. In the partial sums register similarly the least significant digit is to be considered to be in the units position and the most significant to have reversed sign and to appear 63 pulses later. In order to keep track of which part of the partial sum is available at any moment we have a signal ODD which is stimulated during the first minor cycle of the stimulation of S, and thereafter in alternate minor cycles so long as S is stimulated. When the multiplicand is taken from TS 3 we have to make some slight modifications to it before it is in suitable condition for adding into the partial sum. We have to convert the periodic signal with period 32 or 34 into a sequence of 64 digits of which 32 form the original content of TS 3, and the rest is a sort of padding. We may call the 32 digits the genuine digits. Those digits of padding which are less significant than the genuine digits are to be all zero, those which are more significant are to be the same as the most significant genuine digit. It will be seen that this modified multiplicand MUCAND 2 has the same meaning as the original multiplier, but expressed in the code which is appropriate to the partial sum, and multiplied by the power of 2 which is required at the time. It may be necessary to change the sign of this multiplicand, if POS was not stimulated. A simple circuit will do this (Fig. 34).
Owing to the fact that the partial sums register is a closed cycle of 64 there is a danger of carries from the most significant digit on to the least significant. This has to be prevented, and it is done by suppressing the carry in the appropriate adder at the time P32 & -ODD. This is shown by an inhibiting connection on to the adder.
The detailed correctness of the circuits is best verified by working through various particular cases. It is necessary to work several different ones in order to bring out the various different special points involved. In Fig. 35 the preliminaries to a long multiplication have been worked. This shows the setting up of the new CI and the transfer of digits to the valve elements Z1, Z2, Z3, Z4. It brings out the point of adding 2 rather than 1 to the CD in cases A, B, for we are just in time to catch the next instruction. The final stages of the multiplication are shown in Fig. 36. Here it has been assumed that the minor cycle is of length 16, in order to reduce the space occupied by the working.